1. Field
Various embodiments of the present invention relate to a semiconductor design technology, and more particularly, to testing semiconductor devices.
2. Description of the Related Art
In general, semiconductor devices pass through various types of tests before shipment, and the operations of the semiconductor devices are verified through the tests.
When various types of tests are performed on a semiconductor device, failure information is generated during each of the tests. Based on the failure information, the semiconductor device may be repaired in various manners to correct the failures so that the device performs operations normally.
As described above, various types of tests need to be performed, and various pieces of failure information may be generated whenever one test is performed. However, it may be very inefficient to repair the semiconductor device by immediately providing failure information whenever each test is completed.
Thus, a plurality of tests are sequentially and intensely performed, plural pieces of failure information generated at each of the tests are collectively stored in a specific storage, and repair operations for the respective tests are then performed.
FIG. 1 is a diagram for describing a conventional method for storing test failure information in a storage space included in a tester.
For reference, FIG. 1 illustrates a method for storing information on a plurality of defective memory cells in a semiconductor memory device such as DDR SDRAM. However, this is an example, and various pieces of failure information may occur during a test process for the semiconductor device.
Since a plurality of memory cells are arranged in array, a row address and a column address are needed to specify a defective memory cell in which a failure occurred.
Thus, the conventional method stores a row address and a column address of the defective memory cell in storage of test equipment.
While a plurality of tests are performed on a plurality of memory cells, failure determinations may be repetitively made on the same memory cell.
However, since a plurality of tests are sequentially and intensely performed, row addresses and column addresses of memory cells that fail any of the tests are stored, regardless of whether the respective pieces of failure information overlap each other.
Thus, the row addresses and the column addresses indicating the same memory cells may be repetitively stored. For example, referring to FIG. 1, column/row addresses 1/2, 4/4, and 7/8 are determined to be failure addresses and stored at the first test. Then, column/row addresses 1/2, 4/4, and 7/8 are determined to be failure addresses and stored again at the second test. This occurs since an error is highly likely to repetitively occur in a defective memory cell when applying plural tests.
When plural pieces of failure information generated during the respective tests are repetitively stored, storage space for storing the failure information needs to be increased resulting in the test cost inevitably increasing.